Comparison study of Drain Current, Subthreshold Swing and DIBL of III-V Heterostructure and Silicon Double Gate MOSFET

We investigate the performances of 18 nm gate length AlInN/GaN, InP/InGaAs heterostructure and a Silicon double gate MOSFET, using 2D Sentaurus TCAD simulation. The heterostructure device uses lattice-matched wideband Al0.83In0.17N /InP and narrowband GaN / In0.53Ga0.47As layers, along with high-k Al2O3 as the gate dielectric, while silicon based device uses SiO2 gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the density gradient model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity in heterostructure devices, the maximal drain current density achieved is very high. Extensive performance evaluation of the major device has been carried outusing the metrics such as Drain Induced Barrier Lowering (DIBL) and subthreshold slope (SS) for a wide range of gate lengths. The proposed AlInN/GaN and InP/ InGaAs heterostructure DG MOSFET shows anexcellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.